1. Field of the Invention
The present invention relates to a plasma display panel, and more particularly, to a plasma display panel and method of driving same, wherein the application time point and width of a pulse applied during the address period of a sub-field are improved to reduce noise and prevent degradation of jitter characteristics.
2. Background of the Related Art
Generally, in a plasma display panel, barrier ribs formed between a front substrate and a rear substrate form unit or discharge cells. Each of the cells is filled with a main discharge gas, such as neon (Ne), helium (He), or a mixture of Ne and He, and an inert gas containing a small amount of xenon. When it is discharged by a high frequency voltage, the inert gas generates vacuum ultraviolet rays, which thereby cause phosphors formed between the barrier ribs to emit light, thus displaying an image. Because the plasma display panel can be made with a thin and/or slim form, it has attracted attention as a next-generation display device.
FIG. 1 is a perspective view illustrating the configuration of a conventional plasma display panel. As shown in FIG. 1, the plasma display panel includes a front substrate 100 and a rear substrate 110 disposed parallel to each other with a gap in-between. The front substrate 100 has a plurality of electrode pairs arranged on a front glass 101, which serves as the display surface. Each electrode pair is formed of a scan electrode 102 and a sustain electrode 103. The rear substrate 110 is provided with a plurality of address electrodes 113 arranged on a rear glass 111, which constitutes a rear surface. The address electrode 113 is formed so as to cross the electrode pairs 102 and 103.
Both the scan electrode 102 and the sustain electrode 103 are formed of a transparent electrode “a” made of a transparent ITO material and a bus electrode “b” made of a metallic material. The scan electrode 102 and the sustain electrode 103 are covered with one or more upper dielectric layers 104 to limit discharge current and provide insulation among the electrode pairs. A protection layer 105 having magnesium oxide (MgO) deposited thereon in order to facilitate a discharge condition is formed on top of the upper dielectric layer 104.
In the rear substrate 110, barrier ribs 112 are arranged in the form of a stripe pattern (or a well type) such that a plurality of discharge spaces or discharge cells are formed in parallel. Furthermore, a plurality of address electrodes 113 for performing an address discharge to generate vacuum ultraviolet rays are disposed parallel to the barrier ribs 112. The top surface of the rear substrate 110 is coated with R, G, and B phosphors 114 for emitting visible rays for an image display when an address discharge is carried out. A lower dielectric layer 115 is formed between the address electrodes 113 and the phosphors 114 for protecting the address electrodes 113.
The plasma display panel includes a plurality of discharge cells in a matrix formation, and is provided with a driving module (not shown) having a driving circuit for supplying a predetermined pulse to the discharge cells. The interconnection between the plasma display panel and the driving module is illustrated in FIG. 2.
As illustrated in FIG. 2, the driving module includes, for example, a data driver integrated circuit (IC) 20, a scan driver IC 21, and a sustain board 23. The data driver IC 20 supplies a data pulse to the plasma display panel 22 after an image signal is processed. Also, the plasma display panel receives a scan pulse and a sustain pulse output from the scan driver IC 21 and a sustain signal output from the sustain board 23. A discharge is generated in a cell selected by the scan pulse among the plurality of the cells included in the plasma display panel 22, which has received the data pulse, the scan pulse, the sustain pulse, and the like. The cell where discharge has occurred emits light with a predetermined brightness. The data driver IC 20 outputs a predetermined data pulse to each of the address electrodes X1 to Xn through a connector such as a FPC (Flexible Printed Circuit) (not shown). In this case, the X electrodes refer to the data electrodes.
FIG. 3 illustrates a method for implementing image gradation or gray scale in a conventional plasma display panel. As illustrated in FIG. 3, a frame is divided into a plurality of sub-fields having a different number of emission times. Each sub-field is subdivided into a reset period (RPD) for initializing all the cells, an address period (APD) for selecting the cell(s) to be discharged, and a sustain period (SPD) for implementing the gray scale according to the number of discharges. For example, if an image with 256 gradation levels is to be displayed, the frame period (for example, 16.67 ms) corresponding to 1/60 second is divided into eight sub-fields SF1 to SF8, and each of the eight sub-fields SF1 to SF8 are subdivided into a reset period, an address period and a sustain period, as illustrated in FIG. 3.
The reset and address period is the same for every sub-field. However, the sustain period increases by a ratio of 2n (where, n=0, 1, 2, 3, 4, 5, 6, 7) for each sub-field SF1 to SF8, as shown in FIG. 3. Since the sustain period varies from one sub-field to the next, a specific grey level is achieved by controlling which sustain periods are to be used for discharging each of the selected cells, i.e., the number of the sustain discharges that are realized in each of the discharge cells.
FIG. 4 illustrates a driving waveform according to a conventional method for driving a plasma display panel. As shown, during a given sub-field, the waveforms associated with the X, Y, and Z electrodes are divided into a reset period for initializing all the cells, an address period for selecting the cells to be discharged, a sustain period for maintaining discharging of the selected cells, and an erase period for eliminating wall charges within each of the discharge cells.
The reset period is further divided into a set-up and set-down period. During the set-up period, a ramp-up waveform (Ramp-up) is applied to all the scan electrodes at the same time. This results in wall charges of a positive polarity being built up on the address electrodes and the sustain electrodes, and wall charges of a negative polarity being built up on the scan electrodes.
During the set-down period, a ramp-down waveform (Ramp-down), which falls from a positive polarity voltage lower than the peak voltage of the ramp-up waveform to a given voltage lower than a ground level voltage is applied to all the scan electrode at the same time, causing a weak erase discharge within the cells. Furthermore, the remaining wall charges are uniform inside the cells to the extent that the address charge can be stably performed.
During the address period, a scan pulse with a negative polarity is applied sequentially to the scan electrodes, and a data pulse with a positive polarity is selectively applied to specific address electrodes in synchronization with the scan pulse. As the voltage difference between the scan pulse and the data pulse is added to the wall voltage generated during the reset period, an address discharge is generated in the cells to which the data pulse is applied. A wall charge is formed inside the selected cells such that when a sustain voltage Vs is applied a discharge occurs. A positive polarity voltage Vz is applied to the sustain electrodes so that erroneous discharge does not occur with the scan electrode by reducing the voltage difference between the sustain electrodes and the scan electrodes during the set-down period and the address period.
During the sustain period, a sustain pulse is alternately applied to the scan electrodes and the sustain electrodes. Every time a sustain pulse is applied, a sustain discharge or display discharge is generated in the cells selected during the address period.
Finally, during the erase period, (i.e., after the sustain discharge is completed) an erase ramp waveform (Ramp-ers) having a small pulse width and a low voltage level, is applied to the sustain electrodes to erase the remaining wall charges within all the cells.
As discussed above, during the address period the scan pulses and data pulses have the same application time point (i.e., the pulses are applied to the respective electrodes at the same point in time). As illustrated in FIG. 5, according to the conventional driving method, a data pulse is applied to the address electrodes X1 to Xn, at the same time ts that a scan pulse is applied to the scan electrodes. However, when the data pulse and the scan pulse are applied at the same time, noise occurs in the waveforms applied to the scan and sustain electrodes, as illustrated in FIG. 6.
This noise is generated due to coupling through the capacitance of the panel. As illustrated in FIG. 6, noise is generated in the waveforms applied to the scan electrodes and the sustain electrodes at the leading and trailing edges of the data pulse, i.e., when the data pulse abruptly rises and falls. This noise causes the address discharge to become unstable, thereby degrading the driving efficiency of a plasma display panel.